Integrated circuits include design-for-test (DFT) techniques such as logic built-in self-test (or logic BIST) to generate test patterns and detect any potential faults in the integrated circuit. The logic BIST, for example, may include a loading circuit for loading a shift pattern via multiple sequential elements. The logic BIST may include a test module to run multiple tests on the integrated circuit. During the loading of the shift pattern, the shift pattern traverses combinational logic between the sequential elements. As such, the shift operation consumes significant power since the combinational logic toggles data that is sent to the sequential elements. In addition, the combinational logic will require time to settle before the loading circuit may pass the fully loaded shift pattern to subsequent elements of the loading circuit.